Field of the Invention
The present invention relates to a semiconductor memory having serial interface, especially relates to reduction of the power consumption thereof.
FIG. 2 is a view of configuration diagram of the conventional semiconductor memory device.
The above semiconductor memory device is a non-volatile memory being capable of one-time electrical writing and being inputting and outputting address signal or data between inside and outside circuits thereof using serial interface. However, since the present invention relates to read operations thereof, the explanation of write circuits is omitted.
The above semiconductor device includes an address counter 11 for converting an address signal AD in a serial signal SI being provided serially by the outside to parallel data and for holding the above converted data, a row decoder 12 being provided with the upper bits (row address) of the above address signal AD held in the above address counter 11, and a column decoder 13 being provided with the lower bits (column address).
The row decoder 12 decodes the row address from the address counter 11 and drives word lines of a memory-cell matrix 14. Furthermore, the column decoder 13 decodes the column address from the address counter 11 and outputs a select signal to a multiplexer 15.
The memory-cell matrix 14 not shown in figures consists of a plural of word lines placed in parallel, a plural of drain lines placed across the above word lines, and MOS transistors having floating gates placed at the crossing points of the above word lines and the above drain lines as memory-cells. The control gate of the memory-cell is connected to the word line, the drain is connected to the drain line, and the drain is connected to the drain line, the source is connected to the bit-line placed in parallel to the above drain line, and the above bit-line is connected to the multiplexer 15.
The multiplexer 15 selects 16 bit-lines corresponding to the column address out of the bit-lines connected to the memory-cell matrix 14, based on the select signal from the column decoder 13 and connects the above 16 bit-lines to a sense amplifier 16. The sense amplifier 16 amplifies a slight voltage difference arisen between the above selected bit-lines to the predetermined logic level.
A data latch 17 for latching the 16-bit data from the above sense amplifier 16 at the timing of a latch signal LAT is connected to the output side of the sense amplifier 16. Furthermore, an output selector 18 and an output buffer 19 for outputting the 16-bit data held in the data latch 17 at the given timing as a output data DO are connected to the output side of the data latch 17.
Moreover, the aforementioned semiconductor memory device includes a controller 20 for controlling the whole operation based on a chip select signal /CS and a clock signal CK given from the outside, a gate-voltage generating unit 21 for driving the memory-cell matrix 14, and a drain-voltage generating unit 22. The controller 20 outputs an activating signal ACT to the sense amplifier 16, the gate-voltage generating unit 21, the drain-voltage generating unit 22, a latch signal LAT to the data latch 17, timing signals SL0-SL16 to the output selector 18, and a output enable signal OE and output clocks OC, /OC to the output buffer 19.
The gate-voltage generating unit 21 generates a gate-voltage VCW (for example, 3.6V) for driving the selected word lines of the memory-cell matrix 14 while the activating signal ACT is provided. Additionally, the drain-voltage generating unit 22 generates a drain-voltage CDV (for example, 1.0V) given to the drain lines of the memory-cell matrix 14 while the activating signal ACT is provided.
FIG. 3 is a view of a signal waveform diagram showing an example of writing operations in the semiconductor memory device of FIG. 2. The semiconductor memory device thereof is activated by falling of the chip select signal /CS, and then a serial signal SI from the outside is inputted serially synchronized with the rising edge of the clock signal CK. The first 8 bits of the above serial signal SI represents a command signal CMD, and it is assumed that a normal read mode is set in the case hereof. By the above mode setting, the enable signal NRD rises and the activating signal ACT rises. By rising of the activating signal ACT, the gate-voltage generating unit 21 and the drain-voltage generating unit 22 are driven, then the gate-voltage VCW rises from a power-supply voltage VCC to 3.6V and the drain-voltage CDV rises from a ground voltage GND to 1.0V.
An 24-bit address signal AD of address signals A1, A2, A3 following the command signal CMD in the serial signal SI is set into the address counter 11. Subsequently, the address signal AD set in the address counter 11 is divided and provided the row decoder 12 and the column decoder 13, then the corresponding 16-bit address data is read out from the memory-cell matrix 14 through the multiplexer 15. The read data thereof is amplified to the predetermined logic level by the sense amplifier 16 and provided the data latch 17.
When the latch signal LAT from the controller 20 is level “L”, the data is inputted to the data latch 17, and when the latch signal is changed to level “H”, the input data is held therein. The latched data of the data latch 17 is provided the output selector 18 in parallel. From the falling edge of the 32nd clock after address setting by the serial signal SI is finished, the output enable signal OE is set to level “H” and activated, then the output of the output clocks OC. /OC is started.
Furthermore, the timing signals SL0-SL15 are changed to level “L” sequentially, and during the period of the above level “L”, the data of the data latch 17 are sequentially transferred to the output buffer 19 through the output selector 18. The transferred data are serially outputted from the output buffer 19 as the output data DO, synchronized with output clocks OC, /OC.
In every 16 clocks, the value of the address counter 11 is counted up, and the sequential address data of the memory-cell matrix 14 is read out sequentially and serially.
The operation of the normal read mode is explained before, however, there is a high-speed read mode for conducting read operation by faster clock. In the high-speed read mode, the sequence is composed as follows. After the 24-bit address signal AD of the address signals A1, A2, A3 following the command signal CMD is provided, dummy 8-clock cycles are inserted to acquire time for reading the first data, and then the read operation is started. The operations following thereafter are the same as in normal read mode.
Patent document: Japanese Patent Laid-Open Number H6-259320.